Synopsys today introduced the complete DesignWare High-Bandwidth Memory 2 (HBM2) IP solution, which includes controllers, PHYs and authentication IPs, enabling an aggregate bandwidth of 307 GB / s and a DDR4 interface at 3200 Mb / s data transfer rate operation under 12 times. In addition, DesignWare HBM2 IP solution is about 10 times more efficient than DDR4. Advanced graphics, high-performance computing (HPC) and network applications, the need for more memory bandwidth to keep up with high-end process technology brought about by the high computing performance. With the DesignWare HBM2 IP solution, designers can achieve memory requirements with minimal power consumption and low latency. The new DesignWare HBM2 IP solution is based on Sun Microsystems' proven HBM and DDR4 IP, and has proven in thousands of designs and is used in millions of SoCs. The solution allows designers to reduce the risk of integration and accelerate the adoption of new standards.
"We chose Synopsys DesignWare HBM2 IP solution to take full advantage of the 16GB HBM2 memory bandwidth and power-saving features of the Radeon Vega Frontier Edition graphics card," said Joe Macri, AMD's vice president and product technology officer. The high level of memory interface allows us to successfully integrate HBM2 IP into the Vega GPU architecture and achieve more aggressive power and memory bandwidth targets to meet the needs of machine learning and advanced drawing applications. "
The complete DesignWare HBM2 IP solution is uniquely designed to allow designers to meet the memory bandwidth, latency, and power requirements of the design. Whether it is lock step or memory interleaved mode, DesignWare HBM2 controller can support virtual channel operation, the user can according to its special traffic pattern (traffic pattern) will maximize the bandwidth. HBM2 controller and PHY are compatible with DFI 4.0 interface, so that meet the DFI
DesignWare HBM2 PHY IP provides four power management status and fast frequency switching, through the operating frequency (operating frequency) between the rapid conversion, SoC to achieve the purpose of power management. The DesignWare HBM2 PHY achieves a microbump array that conforms to the JEDEC HBM2 SDRAM standard, delivering the shortest 2.5D package path and the highest signal integrity. To simplify the HBM2 SDRAM test, the DesignWare HBM2 PHY IP provides an access loopback mode for the IEEE 1500 port as a link between testing and establishing SoC and HBM2 SDRAM.
Synopsys HBM's VC Verification IP fully complies with the HBM JEDEC specification (including HBM2) and provides communication protocols, methodology, validation and production performance features, including built-in protocol verification, coverage and validation programs, Verdi® protocol awareness ( Protocol-aware debugging and performance analysis, so that users can HBM-based design for rapid verification.
"Increasing the memory bandwidth without increasing power consumption and wafer area is important for graphics cards, HPC and web applications," said John Koeter, vice president of IP marketing at Synopsys. "As a leader in memory IP, "Working with a number of leading customers to develop HBM2 IP solutions to help designers cope with ever-increasing output requirements while improving the latency and energy efficiency of high-performance SoC designs."
Time to market and resources
DesignWare HBM2 PHY and VC verification IP for 14 and 7 nanometer process technologies are available; IP for other process technologies is under development. For more information on DesignWare HBM2 controller IP, please contact Synopsys.
Welcome to the recent webinar: DDR4 or HBM2 high bandwidth memory: how to choose
About DesignWare HBM2 IP
VC Verification of HBM2